The reset strategy. Choose between:

0, reset disabled

1, software reset

2, hardware reset

3, core reset

4, system reset.

The following reset strategies are available, if present in the file specified by ‑‑jet_script_file and defined by corresponding instances of ‑‑reset_style:

5, custom reset

6, reset by watchdog or reset register

7, reset and halt after bootloader

8, reset and halt before bootloader

9, connect during reset

The time in milliseconds that the hardware reset asserts the reset signal (line nSRST/nRESET) low to reset the device.

Some devices might require a longer reset signal than the default 200 ms.

This parameter applies to the hardware reset, and to those custom reset strategies that use the hardware reset.

The delay time, in milliseconds, after the reset signal has been de-asserted, before the debugger attempts to control the processor.

The processor might be kept internally in reset for some time after the external reset signal has been de-asserted, and thus inaccessible for the debugger.

This parameter applies to the hardware reset, and to those custom reset strategies that use the Hardware reset.