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IAR Embedded Workbench for Arm 9.70.x

LDR (64-bit mode)

In this section:
Syntax
LDRregister,=expression
Parameters

register

The register to load, X0–X30 or W0–W30.

expression

Any 32-bit or 64-bit expression. A 64-bit expression can be loaded into X0–X30 and a 32-bit expression can be loaded into W0–W30.

Description

The LDR pseudo-instruction loads a register with any 32-bit or 64-bit expression. The assembler places the constant in a literal pool and generates a program-relative LDR instruction that reads the constant from the literal pool. The offset from the instruction to the constant must be within the range -1 Mbyte to +1 Mbyte.