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IAR Embedded Workbench for RISC-V 3.40

Custom instruction directives

In this section:
Syntax
.insn format, {op2|op7}, operands
Parameters

format

The instruction format of the generated custom instruction. See the table Custom assembler instructions below.

op7 or op2

An unsigned immediate value for either 2-bit or 7-bit operation code, depending on the instruction format.

operands

Depending on the instruction format, these can be:

  • f2–f7: unsigned immediate values for 2-bit to 7-bit function code

  • rd, rs1, rs2, rs3: integer or floating-point destination and source registers (x0–x31 or f0–f31, respectively)

  • rd’, rs1’, rs2’: integer or floating-point compressed instruction-constrained destination and source registers (x8–x15 or f8–f15, respectively)

  • expr: an immediate expression, whose width and sign depends on the instruction format. For some instruction formats, operators are allowed.

Description

These directives generate custom instructions not directly supported by the IAR Assembler for RISC-V. All RISC-V instruction formats are supported.

A custom instruction directive can be used with inline assembler in applications written in C or C++. In combination with an inline function, you can create an intrinsic-like function to use custom architecture extensions.

The bits for immediate values in compressed instructions (16-bit RVC) generally have an instruction-specific format that can differ even for instructions of the same type. All immediate values are copied directly into the bitfield—no rearrangements are performed, unless operators (like %hi) or relocations (see below) are used.

Some of the instructions allow relaxations to be performed by the linker. This can be disabled using the .option norelax directive.

These are the required operands for each instruction format:

Assembler instruction

Relaxed by linker

Resulting instruction format

.insn b op7, f3, rd, rs1, expr

—

Alias for .insn sb

.insn ca op2, f6, f2, rd’, rs2’

—

CA

.insn cb op2, f3, rs1’, expr

—

CB

.insn ci op2, f2, rd, expr

—

CI

.insn ciw op2, f3, rd’, expr

—

CIW

.insn cj op2, f3, expr

—

CJ with RISCV_RVC_JUMP relocation

.insn cr op2, f4, rd, rs1

—

CR

.insn cs op2, f3, rs1’, rs2’, expr

—

CS

.insn i op7, f3, rd, rs1, expr

—

I, with relocations depending on expr (like ADDI)

.insn i op7, f3, rd, expr(rs1)

—

I, with relocations like LW

.insn r op7, f3, f7, rd, rs1, rs2

—

R

.insn r op7, f3, f2, rd, rs1, rs2, rs3

—

Alias for .insn r4

.insn r4 op7, f3, f2, rd, rs1, rs2, rs3

—

R4

.insn s op7, f3, rd, expr(rs1)

If %lo is used

S, with relocations like SW

.insn sb op7, f3, rd, rs1, expr

—

B, with RISCV_BRANCH relocation

.insn sb op7, f3, rd, expr(rs1)

—

Alias for .isns s

.insn u op7, f3, rd, expr

If %hi is used

U, with relocations like LUI included

.insn uj op2, rd, expr

—

J, with RISCV_JAL relocation

Table 132. Custom assembler instructions 


Refer to the RISC-V ISA specification, sections 2.3 and 12.2, for details on bit layout.

The operating code (op2/op7) can be supplied as an assembler constant expression, or as one of:

Operation code

Value

AMO

0x2f

AUIPC

0x17

BRANCH

0x63

C0

0x0

C1

0x1

C2

0x2

CUSTOM_0

0x0b

CUSTOM_1

0x2b

CUSTOM_2

0x5b

CUSTOM_3

0x7b

JAL

0x6f

JALR

0x67

LOAD

0x03

LOAD_FP

0x07

LUI

0x37

MADD

0x43

MISC_MEM

0x0f

MSUB

0x47

NMADD

0x4f

NMSUB

0x4b

OP

0x33

OP_32

0x3b

OP_FP

0x53

OP_IMM

0x13

OP_IMM_32

0x1b

STORE

0x23

STORE_FP

0x27

SYSTEM

0x73

Table 133. Constant value alternatives to opcodes 


Examples

These lines of code show how to use these directives:

.insn i 0x13, 0x3, a0, a1, 0x40 // equivalent to
                                // sltiu a0, a1, 0x40
.insn s 0x23, 0, a0, 4(a1       // equivalent to sb a0, 4(a1)
.insn s STORE 0, a0, 4(a1)      // equivalent to sb a0, 4(a1)
.insn s STORE 1, a0, %lo12(my_symbol)(a1)
                               // equivalent to
                               // sh a0,%lo12(my_symbol)(a1)

The .insn directives can also be used in inline assembler:

int insn_example(int lhs, int rhs)
{
    int res;
    __asm(".insn r 0x33, 0x7, 0x0, %0, %1, %2" :
          "=r"(res) : "r"(lhs), "r"(rhs) );
          // generates AND r, r, r
    return res;
}