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IAR Embedded Workbench for RISC-V 3.40

Supported RISC-V devices

In this section:

The IAR C/C++ Compiler for RISC-V supports these standard extensions to the RISC-V architecture:

  • Standard extension for Integer Multiplication and Division (M)

  • Standard extension for Atomic Instructions (A)

  • Standard extensions for Single-Precision Floating-Point operations on dedicated floating-point registers (F) and on integer registers (Zfinx)

  • Standard extensions for Double-Precision Floating-Point operations on dedicated floating-point registers (D) and on integer registers (Zdinx)

  • Standard extension for Compressed Instructions (C)

  • Standard extension for Bit Manipulation (B)

    (Zba, Zbb, Zbc, and Zbs)

  • Standard extension for Packed-SIMD Instructions (P), including the three subsets Zbpbo, Zpfsoperand, and Zpn

  • Standard extension for User-Level Interrupts (N)

  • Standard extensions for Cache Maintenance Operations (CMO): Zicbom, Zicbop, and Zicboz

In addition, the non-standard AndeStar™ extensions CoDense, DSP, and V5 Performance are supported, as well as the Eswin DSP extension and the Nuclei DSP extension.

The RV32I, RV32E, and RV64I base integer instruction sets are supported.

Danger

Use the ‑‑core option to select the architecture extensions for which the code will be generated, see ‑‑core.

Caution

In the IDE, choose Project>Options>General Options>Target and choose your device from the Device drop-down list. The supported architecture extensions will then be automatically selected.