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IAR Embedded Workbench for RISC-V 3.40

Code Generation

In this section:

The Code Generation options determine the code model, the heap and stack sizes, misaligned data access, and the initialization of the interrupt vector table.

EWOptionsCodeGen_RISCV_03.png

For more information about code models and using the stacks and heaps, see Code models (RV64 only) , Storage of auto variables and parameters, and Dynamic memory on the heap.

Code model

The code model controls how generated code and data is addressed and linked. For RV32 devices, Medlow is the only available code model. For RV64 devices, choose between:

Medlow

The generated code can be up to 2 Gbytes and must lie between absolute addresses –8000'0000 and +8000'0000.

Medany

The generated code can be up to 2 Gbytes, placed within any single 2 Gbytes address range anywhere in memory.

Stack size

Specify the stack size.

Heap size

Specify the heap size.

Allow misaligned data accesses

Makes it possible for the compiler and the linker to access misaligned data objects. For information about misaligned data accesses, see ‑‑allow_misaligned_data_access.

Automatic setup of interrupt vector table

Makes the linker add startup code that initializes the interrupt vector table before the execution reaches the main function. For information about the interrupt vector table, see Interrupt vectors and the interrupt vector table.

Note

This option is not available for all devices.