Introduction to performance monitoring
Briefly about performance monitoring
The Performance Monitoring window is a viewer for counting events or CPU clock cycles through the Performance Monitoring Unit (PMU) available on Cortex-A, Cortex-R, and some Cortex-M devices. Cortex-M devices must be based on the Armv8.1M architecture.
To monitor event counters or CPU cycles through the PMU in the Performance Monitoring window, you must first make settings in the window and select the events that you want to monitor.
Requirements and restrictions for using performance monitoring
To use performance monitoring in your hardware debugger system, consider these requirements and restrictions:
This feature requires an I-jet or J-Link probe.
The target device must be equipped with a PMU. There are different PMU protocol versions available. C-SPY can handle all versions from PMUv1 and higher.
Note: The PMU on Arm v8-A (or higher) devices is not supported by the C-SPY Performance Monitoring window.
To use Auto-Update on a Cortex-A or Cortex-R device, IAR Embedded Workbench also requires a probe with a driver that can connect to the PMU through a debug access point (DAP)—currently only available with the I-jet family of probes—and the target must have memory-mapped registers. If these requirements are not met, the values of the event counters will only be updated when the application execution is stopped. For a Cortex-M device equipped with a PMU, DAP is not required for enabling Auto-Update, but currently only the I-jet family of probes are officially supported by C-SPY.
Warning
When the Performance Monitoring window is open, the PMU registers in the Registers window (if visible) cannot be modified and their values cannot be reliably synced with the values in the Performance Monitoring window.
Note
For Armv7 and Armv8 devices, the PMU counters use 32-bit registers (for Armv8.1M devices, the PMU counters only use 16-bit registers), but the values in the Performance Monitoring window will show 64-bit data, taking into account counter overflows.
Event types
The PMU is designed to count different types of events. There are two categories of events—common events and implementation-defined events.
Common events
If implemented, a common event must comply with the definitions given by the Arm Architecture specification. The Performance Monitoring window provides a standard list of these events. If a common event is not implemented in the target device, the counter will not increment. Therefore, you are responsible for knowing whether or not an event has been implemented in the device you are using.
Implementation-defined events
An implementation-defined event is more dependent on the target device, which gives the chip manufacturer more freedom in the design. However, Arm strongly recommends that the implementation conforms to the definitions in the Arm Architecture specification.
The implementation-defined event list in C-SPY can contain events specific to the current device. The Performance Monitoring window manages functions for loading and saving this list as a text file that you can create and modify. Examples of architecture specific implementation-defined event lists are provided in the directory arm\src\PMU. This list is also automatically saved in the project settings file in the current IAR Embedded Workbench project folder when C-SPY exits.
Detecting counter overflow
Counter overflow occurs when the highest bit (bit 31 on 32-bit registers) in a PMU counter changes from 1 to 0. This change can be seen in the PMOVSR register in 32-bit mode, and in the PMOVSR_EL0 register in 64-bit mode (which is only available for Armv8 devices). For Armv8.1M devices, the register is named PMU_OVSR.
If Auto-Update is enabled, the overflows will be incremented when detected, and shown in the Overflow column in the Performance Monitoring window.
If Auto-Update is disabled, C-SPY will not be able to keep track of the overflows, which makes the values of the counters in the Value column unreliable. Whenever the execution is paused and an overflow is detected in a counter, there is no way for C-SPY to know if there has been more than one overflow during execution. In general, the values in the Value column are unreliable whenever the corresponding counters show a value less than zero (0) in the Overflow column.
Occasionally, a value in the Value column might show an asterisk (*) before the actual value and a tooltip with the word Overflow when the mouse pointer hovers over the affected counter value. This indicates that the overflow bit for that counter is set, but C-SPY has not yet updated the value and incremented the overflow count in the Overflow column.